1. Field of the Invention
The present invention relates to a semiconductor device comprising an n-channel type insulated gate field effect transistor (herein after abbreviated as xe2x80x9cMISFETxe2x80x9d) and p-channel type MISFET with short gate lengths and relates to a method manufacturing the semiconductor device.
2. Description of the Related Art
MISFET has highly been integrated and improved to have high speed by making the configuration fine based on the scaling law.
In terms of example, it is required to make a gate insulating film as thin as 2 nm or thinner in a MISFET with 0.1 xcexcm or shorter gate length. In the case a polycrystalline silicon film used as a constituent material for a gate electrode, a capacity is formed in the gate electrode in such a fine structure by depletion of impurities. Further, carrier quantization occurring in a channel inversion layer forms a capacity. Such capacities are formed in series in relation to the gate insulating film MOS capacity and therefore, the gate capacity is considerably lowered. It is possible to suppress the capacity attributed to the depletion among those capacities by using a metal for a constituent material of the gate electrode. In that case, in order to suppress the reaction of the gate metal film and the gate insulating film at the time of thermal treatment, it is necessary to form a barrier film with high conductivity between the gate metal film and the gate insulating film. A high melting point metal nitride such as titanium nitride, tungsten nitride or tantalum nitride may generally be used for the barrier film.
Further, the cross-section of the gate electrode and a diffusion layer is narrowed following the scaling to result in high sheet resistance of them and difficulty of fabrication of semiconductor device with high speed and excellent capability. In so far as the gate length is 0.12 xcexcm, the countermeasure to deal with this problem is to employ salicide technique, that is, self-alignment silicide technique which involves process of forming a high melting point metal film e.g. a titanium film or a cobalt film on a polycrystalline silicon film and/or on a diffusion layer and making the metal film a silicide to form a high melting point metal silicide film and a high melting point metal silicide layer on the surface of them.
However, in the generation in which the gate length is narrowed to 0.1 xcexcm or shorter, it has become hard to lower the resistance by the foregoing technique, because in an ultra-fine wire layer, the reaction of conversion into silicide is unreliable.
It becomes, therefore, effective to employ a metal film with a lower resistivity than that of a high melting point metal silicide film in order to lower the resistance of the gate electrode. Especially, in order to avoid increase of resistivity by post heating treatment, a high melting point metal film is required to be used as the metal film. The high melting point metal to be used is generally titanium, tungsten or tantalum. In order to suppress the reaction of the high melting point metal film of the gate electrode and the gate insulating film by the foregoing heating treatment, it is required to form a barrier film with a high conductivity between the high melting point metal film of the gate electrode and the gate insulating film.
The configuration of a complementary type MISFET comprising a high melting point metal film of the gate electrode and its fabrication method will be described in reference to FIG. 1A to FIG. 1C, which are cross-sectional views of manufacturing process steps of the semiconductor device.
First of all, an element separation region 402 is formed on the surface of a silicon substrate 401 and an n-type well region 403 and a p-type well region 404 are formed. A gate oxide film 405 is formed by thermal oxidation on the n-type well region 403 and the p-type well region 404. A titanium nitride film 406, a tungsten film 407, and a hard mask film 408 of a first insulating film are successively formed on the whole surface (FIG. 1A).
Then, the above described hard mask film 408, tungsten film 407, and titanium nitride film 406 are successively patterned by anisotropic etching to form a first gate electrode 409 with a layered structure of the titanium nitride film 406 and the tungsten film 407 on the surface of the n-type well 403 and to form a second gate electrode 410 with a layered structure of the titanium nitride film 406 and the tungsten film 407 on the surface of the p-type well 404. Following that, an n-type source/drain extension region 411 and a p-type pocket region 412 are formed on the surface of the p-type well region 404 by ion implantation of n-type impurities and ion implantation of p-type impurities using the gate electrode 410 as a mask. In the same manner, a p-type source/drain extension region 413 and an n-type pocket region 414 are formed on the surface of the n-type well region 403 by ion implantation of p-type impurities and ion implantation of n-type impurities using the gate electrode 409 as a mask (FIG. 1B).
Next, a second insulating film formed on the whole surface is etched back to form side wall spacers 415 covering the side faces of the gate electrodes 409, 410. Following that, an n+-source/drain region 416 is formed on the surface of the p-type well 404 by ion implantation of n-type impurities using the side wall spacers 415 and the gate electrode 410 as a mask. In the same manner, a p+-source/drain region 417 is formed on the surface of the n-type well 403 by ion implantation of p-type impurities using the side wall spacers 415 and the gate electrode 409 as a mask. Successively, for example, a titanium film is formed on the whole surface and made to be silicide to form a titanium silicide layer 418 respectively on the n+-source/drain region 416 and p+-source/drain region 417 (FIG. 1C). After that, though being not illustrated, an interlayer insulating film or the like is formed on the whole surface to complete a conventional semiconductor device comprising a complementary type MISFET.
However, the absolute values of threshold voltage values of the foregoing n-channel type MISFET comprising the gate electrode 410 and the foregoing p-channel type MISFET comprising the gate electrode 409 are unfavorably increased as compared with those of an n-channel type MISFET comprising a gate electrode made of an n+-type polycrystalline silicon film and a p-channel type MISFET comprising a gate electrode made of a p+-type polycrystalline silicon film. That is attributed to that the Fermi level of a high melting point metal nitride generally exists between the lower end of the conduction band and the upper end of the filled band of silicon. The increase of the absolute value of the threshold voltage results in decrease of the operation speed of a complementary MISFET.
In general, the threshold voltage in a MISFET comprising a gate electrode made of polycrystalline silicon film is controlled by doping a surface part of a silicon substrate to be a channel region with an impurity to be a donor or an acceptor. However, such control of the threshold voltage by doping with an impurity is impossible for a MISFET having a gate electrode with a layered structure comprising a high melting point metal nitride film and a high melting point metal film.
Accordingly, one object of the present invention is to provide semiconductor devices each having a gate electrode structure capable of suppressing increase of the absolute value of the threshold voltage of at least either an n-channel or a p-channel in a complementary type MISFET.
Another object of the present invention is to provide methods of manufacturing the semiconductor device having such a gate electrode structure.
According to one feature of the present invention, there is provided a semiconductor device which comprises a silicon substrate, an n-type well and a p-type well separated from each other by an element separation region and formed on the surface of the substrate. A p-channel type MISFET having a first gate electrode and formed on the n-type well, an n-channel type MISFET having a second gate electrode and formed on the p-type well. The first gate electrode is formed on the surface of the n-type well by interposing a first gate oxide film. The first gate electrode includes a first conductive film of a nitride of a first high melting point metal directly coating the surface of the first gate oxide film and a second high melting point metal film formed on the surface of the first conductive film. The second gate electrode formed on the surface of the p-well by interposing a second gate oxide film. The second gate electrode includes a second conductive film of a nitride of the first high melting point metal with higher nitrogen content than that of the first conductive film and directly coating the surface of the second gate oxide film and a metal film formed on the surface of the second conductive film. Preferably, the side faces of the above described first and second gate electrodes are directly covered with side wall spacers, respectively. The first and second gate oxide films are thermal oxidation films and the metal film constituting the second gate electrode is the above described second high melting point metal film and the above described first high melting point metal is one of titanium, tungsten and tantalum. Further, preferably, the side faces of the first gate electrode are directly covered with side wall spacers and the side faces of the second gate electrode are covered with the side wall spacers through the second gate oxide film and the above described first high melting point metal is one of titanium, tungsten and tantalum.
Furthermore, the crystal orientation of said second conductive film might differ from that of the first conductive film.
Further feature of the present invention, there is provided a semiconductor device which comprises a silicon substrate, an n-type well and a p-type well separated from each other by an element separation region and formed on the surface of the substrate, a p-channel type MISFET having a first gate electrode and formed on the n-type well, an n-channel type MISFET having a second gate electrode and formed on the p-type well, and side wall spacers of respectively insulating films coating the side faces of the first and second gate electrodes. The first gate electrode is formed on the surface of the n-type well through a first gate oxide film formed by thermal oxidation, and includes a first conductive film of a nitride of a first high melting point metal directly coating the surface of the first gate oxide film and a second high melting point metal film formed on the surface of the first conductive film. The second gate electrode is formed on the surface of the n-well through a second gate insulating film containing nitrogen, and includes nitride of the first high melting point metal with higher nitrogen content than that of the first conductive film and directly coating the surface of the second gate insulating film and a metal film formed on the surface of the second conductive film. Side faces of the first gate electrode are directly coated with the side wall spacers and the side faces of the second gate electrode are coated with the side wall spacers through the gate insulating film. Preferably the gate insulating film is either a silicon nitride film or a silicon nitride oxide film. The first high melting point metal may be one selected from titanium, tungsten and tantalum.
Yet further feature of the present invention, there is provided a semiconductor device which comprises a silicon substrate, an n-type well and a p-type well separated from each other by an element separation region and formed on the surface of the substrate, a p-channel type MISFET having a first gate electrode and formed on the n-type well, an n-channel type MISFET having a second gate electrode and formed on the p-type well, and side wall spacers of respectively insulating films coating the side faces of the first and second gate electrodes. The first gate electrode is formed on the surface of the n-type well through a gate oxide film formed by thermal oxidation, and includes a first conductive film of a nitride of a first high melting point metal directly coating the surface of the gate oxide film and a second high melting point metal film formed on the surface of the gate oxide film. The second gate electrode is formed on the surface of the n-well through a gate insulating film, and includes a second conductive film of a nitride of a third high melting point metal different from the first high melting point metal and directly coating the surface of the gate insulating film and a metal film formed on the surface of the second conductive film. Side faces of the first gate electrode are directly coated with the side spacers and the side faces of the second gate electrode are coated with the side spacers through the gate insulating film. Preferably the first high melting point metal is titanium and the third high melting point metal is tantalum.
According to one feature of another aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprises the steps of: forming an n-type well and a p-type well separated from each other by an element separation region on the surface of a silicon substrate and forming a gate oxide film on the surface of the n-type well and p-type well by thermal oxidation; forming a conductive film of a nitride of a first high melting point metal on the whole surface, forming a mask film pattern covering the surface of the n-type well and ion-implanting nitrogen in the conductive film using the mask film pattern as a mask; and successively forming a second high melting point metal film and hard mask film of a first insulating film on the whole surface and successively patterning the hard mask film, the second high melting point metal film and the conductive film by anisotropic etching to form a first and a second gate electrodes on the surface of the n-type well and the p-type well, respectively. Preferably the first high melting point metal is one selected from titanium, tungsten and tantalum.
Further feature of another aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprises the steps of: forming an n-type well and a p-type well separated from each other by an element separation region on the surface of a silicon substrate and forming a first gate oxide film on the surface of said n-type well and p-type well by thermal oxidation; forming a first conductive film of a nitride of a first high melting point metal on the whole surface by reactive sputtering in a first nitrogen gas flow rate and further successively forming a second high melting point metal film and hard mask film of a first insulating film; successively patterning the hard mask film, the second high melting point metal film and the conductive film by anisotropic etching to form a first gate electrode on the surface of the n-type well and at the same time to form a temporary gate electrode on the p-type well; forming a second insulating film on the whole surface, forming side wall spacers respectively coating the side faces of the first gate electrode and the temporary gate electrode by etching back the second insulating film; forming a p+-type source/drain region on the surface of the n-type well by ion implantation of p-type impurities using the first gate electrode and side wall spacers as a mask, forming an n+-type source/drain region on the surface of the p-type well by ion implantation of n-type impurities the temporary gate electrode and side wall spacers as a mask, forming a third high melting point metal film on the whole surface and forming a high melting point metal silicide layer in a self-alignment manner on the surface of the p+-type source/drain region and the n+-type source/drain region; forming an interlayer insulating film on the whole surface and carrying out chemical-mechanical polishing (CMP) of the interlayer insulating film until the upper face of the hard mask film is exposed; forming a mask film pattern covering the surface of the n-type well and successively removing the hard mask film, the temporary gate electrode and the first gate oxide film by etching using said mask film pattern as a mask; forming a second gate oxide film on the whole surface by a chemical vapor deposition method; forming a second conductive film of a nitride film of a first high melting point metal by reactive sputtering in a second nitrogen gas flow rate higher than the first nitrogen gas flow rate, and successively forming a metal film on the whole surface; and carrying out CMP of the metal film, the second conductive film and the second gate oxide film until the upper face of the interlayer insulating film is exposed. Preferably the first high melting point metal is one selected from titanium, tungsten, and tantalum. Further preferably, the foregoing second nitrogen gas flow rate is so set as to make the crystal orientation of the second conductive film different from the crystal orientation of the first conductive film. Furthermore, the first high melting point metal is one selected from titanium, tungsten and tantalum.
Yet further feature of another aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprises the steps of: forming an n-type well and a p-type well separated from each other by an element separation region on the surface of a silicon substrate and forming a gate oxide film on the surface of said n-type well and p-type well by thermal oxidation; forming a first conductive film of a nitride of a first high melting point metal on the whole surface and further successively forming a second high melting point metal film and hard mask film of a first insulating film; successively patterning the hard mask film, the second high melting point metal film and the conductive film by anisotropic etching to form a first gate electrode on the surface of the n-type well and at the same time to form a temporary gate electrode on the p-type well; forming a second insulating film on the whole surface, forming side wall spacers respectively coating the side faces of said first and temporary gate electrodes by etching back the second insulating film, forming a p+-type source/drain region on the surface of the n-type well by ion implantation of p-type impurities using the first gate electrode and side wall spacers as a mask, forming an n+-type source/drain region on the surface of the p-type well by ion implantation of n-type impurities using the temporary gate electrode and side wall spacers as a mask, forming a third high melting point metal film on the whole surface and forming a high melting point metal silicide layer in a self-alignment manner on the surface of the p+-type source/drain region and n+-type source/drain region; forming an interlayer insulating film on the whole surface and carrying out CMP of the interlayer insulating film until the upper face of the hard mask film is exposed; forming a mask film pattern covering the surface of the n-type well and successively removing the hard mask film, the temporary gate electrode and the first gate oxide film by etching using the mask film pattern as a mask; forming a gate insulating film containing nitrogen on the whole surface by a chemical vapor deposition method; successively forming a second conductive film of a nitride film of a first high melting point metal and a metal film on the whole surface; diffusing nitrogen in the second conductive film from the gate insulating film by heating; and carrying out CMP of the metal film, the second conductive film and the second gate oxide film until the upper face of the interlayer insulating film is exposed and forming a second gate electrode on the surface of the p-type well. Preferably the first high melting point metal is one selected from titanium, tungsten, and tantalum.
More further feature of another aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprises the steps of: forming an n-type well and a p-type well separated from each other by an element separation region on the surface of a silicon substrate and forming a gate oxide film on the surface of the n-type well and p-type well by thermal oxidation; forming a first conductive film of a nitride of a first high melting point metal on the whole surface and further successively forming a second high melting point metal film and hard mask film of a first insulating film; successively patterning the hard mask film, the second high melting point metal film and the conductive film by anisotropic etching to form a first gate electrode on the surface of said n-type well and at the same time to form a temporary gate electrode structure on the p-type well; forming a second insulating film on the whole surface, forming side wall spacers respectively coating the side faces of the first electrode and temporary gate electrode by etching back the second insulating film, forming a p+-type source/drain region on the surface of said n-type well by ion implantation of p-type impurities using the first gate electrode and side wall spacers as a mask, forming an n+-type source/drain region on the surface of the p-type well by ion implantation of n-type impurities using the temporary gate electrode and sidewall spacers as a mask, forming a third high melting point metal film on the whole surface and forming a high melting point metal silicide layer in a self-alignment manner on the surface of the p+-type source/drain region and n+-type source/drain region; forming an interlayer insulating film on the whole surface and carrying out CMP of the interlayer insulating film until the upper face of said hard mask film is exposed; forming a mask film pattern covering the surface of said n-type well and successively removing the hard mask film, the temporary gate electrode and the gate oxide film by etching using the mask film pattern as a mask; forming a gate insulating film on the whole surface by a chemical vapor deposition method; forming a second conductive film of a nitride film of a fourth high melting point metal and further a metal film on the whole surface; and forming a second gate electrode on the surface of the p-type well by carrying out CMP of the metal film, the second conductive film and the second gate oxide film until the upper face of the interlayer insulating film is exposed. Preferably, the first high melting point metal is titanium and the fourth high melting point metal is tantalum.